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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad5232 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 * 8-bit dual nonvolatile memory digital potentiometer features nonvolatile memory preset maintains wiper settings dual channel, 256-position resolution full monotonic operation dnl < 1 lsb 10 k , 50 k , 100 k terminal resistance linear or log taper settings push-button increment/decrement compatible spi-compatible serial data input with readback function 3 v to 5 v single supply or 2.5 v dual supply operation 14 bytes of user eemem nonvolatile memory for constant storage permanent memory write protection 100-year typical data retention t a = 55 c applications mechanical potentiometer replacement instrumentation: gain, offset adjustment programmable voltage-to-current conversion programmable filters, delays, time constants line impedance matching power supply adjustment dip switch setting general description the ad5232 device provides a nonvolatile, dual-channel, digi tally controlled variable resistor (vr) with 256-position resolution. these devices perform the same electronic adjust- ment function as a potentiometer or variable resistor. the ad5232? versatile programming via a microcontroller allows multiple modes of operation and adjustment. in the direct program mode a predetermined setting of the rdac register can be loaded directly from the microcontroller. another key mode of operation allows the rdac register to be refreshed with the setting previously stored in the eemem register. when changes are made to the rdac register to estab- lish a new wiper position, the value of the setting can be saved into the eemem by executing an eemem save operation. once the settings are saved in the eemem register these values will be automatically transferred to the rdac register to set the wiper position at system power on. such operation is enabled by the internal preset strobe and the preset can also be accessed externally. all internal register contents can be read out of the serial data output (sdo). this includes the rdac1 and rdac2 registers, the corresponding nonvolatile eemem1 and eemem2 regis- ters, and the 14 spare user eemem registers available for constant storage. * patent pending. functional block diagram rdac1 register eemem1 rdac2 register eemem control 14 bytes user eemem eemem2 ad5232 rdac1 rdac2 cs clk wp pr sdi gnd sdo rdy sdo serial interface addr decode v dd v ss a1 w1 b1 a2 w2 b2 sdi the basic mode of adjustment is the increment and decrement command controlling the present setting of the wiper position setting (rdac) register. an internal scratch pad rdac register can be moved up or down one step of the nominal terminal resistance between terminals a and b. this linearly changes the wiper to b terminal resistance (r wb ) by one position segment of the devices?end-to-end resistance (r ab ). for exponential/loga- rithmic changes in wiper setting, a left/right shift command adjusts levels in 6 db steps, which can be useful for audio and light alarm applications. the ad5232 is available in a thin tssop-16 package. all parts are guaranteed to operate over the extended industrial tempera- ture range of ?0 c to +85 c. an evaluation board is available, part number: ad5232eval. code ?decimal 100 75 0 0 25664 percent of nominal end-to-end resistance ?% r ab 128 192 50 25 r wb r wa figure 1. symmetrical rdac operation
rev. 0 C2C ad5232?pecifications electrical characteristics, 10 k , 50 k , 100 k versions ( v dd = 3 v 10% or 5 v 10% and v ss = 0 v, v a = +v dd , v b = 0 v, ?0 c < t a < +85 c unless otherwise noted.) parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode ?specifications apply to all vrs resistor differential nonlinearity 2 r-dnl r wb , v a = nc ? 1/2 +1 lsb resistor nonlinearity 2 r-inl r wb , v a = nc ?.4 +0.4 % fs nominal resistor tolerance r ab ?0 +20 % resistance temperature coefficient r ab / t 600 ppm/ c wiper resistance r w i w = 100 a, v dd = 5.5 v, code = 1e h 5 100 ? r w i w = 100 a, v dd = 3 v, code = 1e h 200 ? potentiometer divider mode ?specifications apply to all vrs resolution n 8 bits differential nonlinearity 3 dnl 1 1/2 +1 lsb integral nonlinearity 3 inl ?.4 +0.4 % fs voltage divider temperature c oefficient v w / t code = half-scale 15 ppm/ c full-scale error v wfse code = full-scale ? 0 % fs zero-scale error v wzse code = zero-scale 0 +3 % fs resistor terminals terminal voltage range 4 v a,b,w v ss v dd v capacitance 5 ax, bx c a,b f = 1 mhz, measured to gnd, code = half-scale 45 pf capacitance 5 wx c w f = 1 mhz, measured to gnd, code = half-scale 60 pf common-mode leakage current 5, 6 i cm v w = v dd /2 0.01 1 a digital inputs and outputs input logic high v ih with respect to gnd, v dd = 5 v 2.4 v input logic low v il with respect to gnd, v dd = 5 v 0.8 v input logic high v ih with respect to gnd, v dd = 3 v 2.1 v input logic low v il with respect to gnd, v dd = 3 v 0.6 v input logic high v ih with respect to gnd, v dd = +2.5 v, 2.0 v v ss = ?.5 v input logic low v il with respect to gnd, v dd = +2.5 v, 0.5 v v ss = ?.5 v output logic high (sdo and rdy) v oh r pull-up = 2.2 k ? to 5 v 4.9 v output logic low v ol i ol = 1.6 ma, v logic = 5 v 0.4 v input current i il v in = 0 v or v dd 2.5 a input capacitance 5 c il 4pf power supplies single-supply power range v dd v ss = 0 v 2.7 5.5 v dual-supply power range v dd /v ss 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd 3.5 10 a programming mode current i dd(pg) v ih = v dd or v il = gnd 35 ma read mode current 7 i dd(xfr) v ih = v dd or v il = gnd 0.9 3 9 ma negative supply current i ss v ih = v dd or v il = gnd, v dd = +2.5 v, v ss = ?.5 v 3.5 10 a power dissipation 8 p diss v ih = v dd or v il = gnd 0.018 0.05 mw power supply sensitivity 5 pss v dd = 5 v 10% 0.002 0.01 %/%
C3C rev. 0 nv/ hz parameter symbol conditions min typ 1 max unit dynamic characteristics 5, 9 bandwidth ? db, bw_10 k ? , r = 10 k ? 500 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k ? 0.022 % thd w v a =1 v rms, v b = 0 v, f = 1 khz, r ab = 50 k ? , 100 k ? 0.045 % v w settling time t s v dd =5v,v ss =0v,v a = v dd , v b = 0 v, v w = 0.50% error band, code 00 h to 80 h for r ab = 10 k ? /50 k ? /100 k ? 0.65/3/6 s resistor noise voltage e n_wb r wb = 5 k ? , f = 1 khz 9 crosstalk (c w1 /c w2 )c t v a = v dd , v b = 0 v, measure v w with adjacent vr making full-scale code change ? nv-s analog crosstalk (c w1 /c w2 )c ta v a1 = v dd , v b1 = 0 v, measure v w1 with v w2 = 5 v p-p @ f = 10 khz, code 1 = 80 h ; code 2 = ff h ?0 db interface timing characteristics applies to all parts 5, 10 clock cycle time (t cyc )t 1 20 ns cs setup time t 2 10 ns clk shutdown time to cs rise t 3 1t cyc input clock pulsewidth t 4 , t 5 clock level high or low 10 ns data setup time t 6 from positive clk transition 5 ns data hold time t 7 from positive clk transition 5 ns cs to sdo-spi line acquire t 8 40 ns cs to sdo-spi line release t 9 50 ns clk to sdo propagation delay 11 t 10 r p = 2.2 k ? , c l < 20 pf 50 ns clk to sdo data hold time t 11 r p = 2.2 k ? , c l < 20 pf 0 ns cs high pulsewidth 12 t 12 10 ns cs high to cs high 12 t 13 4t cyc rdy rise to cs fall t 14 0ns cs rise to rdy fall time t 15 0.1 0.15 ms read/store to nonvolatile eemem 13 t 16 applies to command 2 h , 3 h , 9 h 25 ms cs rise to clock rise/fall setup t 17 10 ns preset pulsewidth (asynchronous) t prw not shown in timing diagram 50 ns preset response time to rdy high t presp pr pulsed low to refreshed wiper positions 70 s flash/ee memory reliability characteristics endurance 14 100 k cycles data retention 15 100 years notes 1 typical parameters represent average readings at 25 c and v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper postions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. i w ~ 50 a @ v dd = 2.7 v and i w ~ 400 a @ v dd = 5 v for the r ab = 10 k ? version, i w ~ 50 a for the r ab = 50 k ? and i w ~ 25 a for the r ab = 100 k ? version. see figure 13. 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = v ss . dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. see figure 14. 4 resistor terminals a, b, w have no limitations on polarity with respect to each other. dual supply operation enables ground-ref erenced bipolar signal adjustment. 5 guaranteed by design and not subject to production test. 6 common-mode leakage current is a measure of the dc leakage from any terminal a, b, w to a common-mode bias level of v dd /2. 7 transfer (xfr) mode current is not continuous. current consumed while eemem locations are read and transferred to the rdac regi ster. see tpc 9. 8 p diss is calculated from (i dd v dd ) + (i ss v ss ). 9 all dynamic characteristics use v dd = +2.5 v and v ss = ?.5 v unless otherwise noted. 10 see timing diagram for location of measured values. all input control voltages are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. switching characteristics are measured using both v dd = 3 v or 5 v. 11 propagation delay depends on value of v dd , r pull_up , and c l . see applications text. 12 valid for commands that do not activate the rdy pin. 13 rdy pin low only for instruction commands 8, 9, 10, 2, 3, and the pr hardware pulse: cmd_8 ~ 1 ms; cmd_9,10 ~ 0.12 ms; cmd_2,3 ~ 20 ms. device operation at t a = ?0 c and v dd < 3 v extends the save time to 35 ms. 14 endurance is qualified to 100,000 cycles as per jedec std. 22 method a117 and measured at v dd = 2.7 v, t a = ?0 c to +85 c, typical endurance at 25 c is 700,000 cycles. 15 retention lifetime equivalent at junction temperature (t j ) = 55 c as per jedec std. 22, method a117. retention lifetime based on an activation energy of 0.6ev will derate with junction temperature as shown in figure 23 in the flash/ee memory description section of this data sheet. the ad5232 contains 9,646 transistors. die size: 69 mil 115 mil, 7,993 sq. mil. specifications subject to change without notice ad5232
rev. 0 C4C ad5232 cpol = 1 t 12 t 13 t 3 t 17 t 9 t 11 t 5 t 4 t 2 t 1 clk t 8 * msb lsb out msb lsb rdy cpha = 1 t 10 t 7 t 6 t 14 t 15 t 16 * not defined, but normally lsb of character previously transmitted. the cpol = 1 microcontroller command aligns the incoming data to the positive edge of the clock. cs sdo sdi figure 2a. cpha = 1 timing diagram t 12 t 13 t 3 t 17 t 9 t 11 t 5 t 4 t 2 t 1 clk cpol = 0 t 8 msb out lsb sdo msb in lsb sdi rdy cpha = 0 t 10 t 7 t 6 t 14 t 15 t 16 * not defined, but normally msb of character just received. the cpol = 0 microcontroller command aligns the incoming data to the positive edge of the clock. * cs figure 2b. cpha = 0 timing diagram
rev. 0 ad5232 C5C ordering guide number of number of end-to-end temperature package package devices per branding * model channels r ab (k ) range ( c) description option container information ad5232bru10 2 10 ?0 to +85 tssop-16 ru-16 96 5232b10 ad5232bru10-reel7 2 10 ?0 to +85 tssop-16 ru-16 1,000 5232b10 ad5232bru50 2 50 ?0 to +85 tssop-16 ru-16 96 5232b50 ad5232bru50-reel7 2 50 ?0 to +85 tssop-16 ru-16 1,000 5232b50 ad5232bru100 2 100 ?0 to +85 tssop-16 ru-16 96 5232bc AD5232BRU100-REEL7 2 100 ?0 to +85 tssop-16 ru-16 1,000 5232bc * line 1 contains adi logo symbol and the data code yyww, line 2 contains detail model number listed in this column. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5232 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 (t a = 25 c, unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v, +7 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v, ? v v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v a , v b , v w to gnd . . . . . . . . . . . . . v ss ?0.3 v, v dd + 0.3 v a x ?b x , a x ?w x , b x ?w x intermittent 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ma digital inputs and output voltage to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v, v dd +0.3 v operating temperature range 3 . . . . . . . . . . . 40 c to +85 c maximum junction temperature (t j max) . . . . . . . . 150 c storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +150 c lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c package power dissipation . . . . . . . . . . . . . (t j max ?t a )/ ja thermal resistance junction-to-ambient ja , tssop-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c/w thermal resistance junction-to-case jc , tssop-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 c/w notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 3 includes programming of nonvolatile memory.
rev. 0 C6C ad5232 pin function descriptions pin number mnemonic description 1 clk serial input register clock pin. shifts in one bit at a time on positive clock edges. 2 sdi serial data input pin. msb loaded first. 3 sdo serial data output pin. open drain output requires external pull-up resistor. commands 9 and 10 activate the sdo output. see table ii. other commands shift out the previously loaded sdi bit pattern delayed by 16 clock pulses. this allows daisy-chain operation of multiple packages. 4 gnd ground pin, logic ground reference. 5v ss negative supply. connect to zero volts for single supply applications. 6 a1 a terminal of rdac1 7 w1 wiper terminal of rdac1, addr(rdac1) = 0 h 8 b1 b terminal of rdac1 9 b2 b terminal of rdac2 10 w2 wiper terminal of rdac2, addr(rdac2) = 1 h 11 a2 a terminal of rdac2 12 v dd positive power supply pin 13 wp write protect pin. when active low, wp prevents any changes to the present register contents, except pr and cmd 1 and 8 will refresh rdac register from eemem. execute a nop instruction before returning wp to logic high. 14 pr hardware override preset pin. refreshes the scratch pad register with current contents of the eemem register. factory default loads midscale 80 h until eemem is loaded with a new value by the user ( pr is activated at the logic high transition). 15 cs serial register chip select active low. serial register operation takes place when cs returns to logic high. 16 rdy ready. active-high open drain output, requires pull-up resistor. identifies completion of commands 2, 3, 8, 9, 10, and pr . top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 clk sdi sdo gnd v ss a1 w1 b1 rdy cs pr wp v dd a2 w2 b2 ad5232 pin configuration
rev. 0 ad5232 C7C operational overview the ad5232 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of v ss < v term < v dd . the basic voltage range is limited to a |v dd ?v ss | < 5.5 v. the digital potentiometer wiper position is determined by the rdac register contents. the rdac register acts as a scratch pad, register allowing as many value changes as necessary to place the potentiometer wiper in the correct position. the scratch pad register can be programmed with any position value using the standard spi serial interface mode by loading the complete representative data word. once a desirable position is found, this value can be saved into a corresponding eemem register. thereafter the wiper position will always be set at that position for any future on-off-on power supply sequence. the eemem save process takes approximately 25 ms, during this time the shift register is locked preventing any changes from taking place. the rdy pin indicates the completion of this eemem save. scratch pad and eemem programming the scratch pad register (rdac register) directly controls the position of the digital potentiometer wiper. when the scratch pad register is loaded with all zeros, the wiper will be connected to the b-terminal of the variable resistor. when the scratch pad register is loaded with midscale code (1/2 of full-scale position), the wiper will be connected to the middle of the variable resis- tor. and when the scratch pad is loaded with full-scale code, all 1s, the wiper will connect to the a-terminal. since the scratch pad register is a standard logic register, there is no restriction on the number of changes allowed. the eemem registers have a program erase/write cycle limitation described in the flash/ eemem reliability section. basic operation the basic mode of setting the variable resistor wiper position (programming the scratch pad register) is accomplished by loading the serial data input register with the command instruc- tion #11, which includes the desired wiper position data. when the desired wiper position is found, the user loads the serial data input register with the command instruction #2, which copies the desired wiper position data into the corresponding nonvola- tile eemem register. after 25 ms the wiper position will be permanently stored in the corresponding nonvolatile eemem location. table i provides an application-programming example listing the sequence of serial data input (sdi) words and the corresponding serial data output appearing at the sdo pin in hexadecimal format. at system power-on, the scratch pad register is refreshed with the value last saved in the eemem register. the factory preset eemem value is midscale. the scratch pad (wiper) register can be refreshed with the current contents of the nonvolatile eemem register under hardware control by pulsing the pr pin. table i. set two digital pots to independent data values then save wiper positions in corresponding nonvolatile eemem registers sdi sdo action b040 h xxxx h loads 40 h data into rdac1 register, wiper w1 moves to 1/4 full-scale position. 20xx h b040 h saves copy of rdac1 register contents into corresponding eemem0 register. b180 h 20xx h loads 80 h data into rdac2 register, wiper w2 moves to 1/2 full-scale position. 21xx h b180 h saves copy of rdac2 register contents into corresponding eemem1 register. be aware that the pr pulse first sets the wiper at midscale when brought to logic zero, and then on the positive transition to logic high, it reloads the dac wiper register with the contents of eemem. many additional advanced programming commands are available to simplify the variable resistor adjustment process. for example, the wiper position can be changed one step at a time by using the software-controlled increment/decrement instruction or, by 6 db at a time, with the shift left/right instruction command. once an increment, decrement, or shift command has been loaded into the shift register, subsequent cs strobes will repeat this command. this is useful for push-button control applications. see the advanced control modes descrip- tion following table i. a serial data output sdo pin is available for daisy chaining and for readout of the internal register contents. the serial input data register uses a 16-bit [instruction/address/data] word. eemem protection write protect ( wp ) disables any changes of the scratch pad register contents regardless of the software commands, except that the eemem setting can be refreshed using commands 8 and pr . therefore, the write-protect ( wp ) pin provides a hard- ware eemem protection feature. execute a nop command before returning wp to logic high. digital input/output configuration all digital inputs are esd-protected high input impedance that can be driven directly from most digital sources. pr and wp , which are active at logic low, must be biased to v dd if they are not being used. no internal pull-up resistors are present on any digital input pins. the sdo and rdy pins are open-drain digital outputs where pull-up resistors are needed only if using these functions. a resistor value in the range of 1 k ? to 10 k ? optimizes the power and switching speed trade-off.
rev. 0 C8C ad5232 serial data interface the ad5232 contains a 4-wire spi-compatible digital interface (sdi, sdo, cs , and clk), and uses a 16-bit serial data word loaded msb first. the format of the spi-compatible word is shown in table ii. the chip select (cs) pin needs to be held low until the complete data word is loaded into the sdi pin. when cs returns high, the serial data word is decoded accord- ing to the instructions in table iii. the command bits (cx) control the operation of the digital potentiometer. the address bits (ax) determine which register is activated. the data bits (dx) are the values that are loaded into the decoded register. table iv provides an address map of the eemem loca tions. the last instruction executed prior to a period of no pro gram- ming activity should be the no operation (nop) instruction. this will place the internal logic circuitry in a minimum power dissipation state. va l i d command counter command processor and address decode serial register clk sdi 5v r pullup sdo gnd pr wp cs ad5232 figure 3. equivalent digital input-output logic the equivalent serial data input and output logic is shown in figure 3. the open-drain output sdo is disabled whenever chip select cs is logic high. the spi interface can be used in two slave modes cpha = 1, cpol = 1 and cpha = 0, cpol = 0. cpha and cpol refer to the control bits, which dictate spi timing in these microconverters and microprocessors: aduc812/aduc824, m68hc11, and mc68hc16r1/916r1. esd protection of the digital inputs is shown in figures 4a and 4b. logic pins v dd gnd inputs 300 ad5232 figure 4a. equivalent esd digital input protection v dd gnd input 300 wp ad5232 figure 4b. equivalent wp input protection daisy chaining operation the serial data output pin (sdo) serves two purposes. it can be used to read out the contents of the wiper setting and eemem values using in struction 10 and 9 respectively. the remaining instructions (#0?, #11?5) are valid for d aisy- chaining multiple devices in simultaneous operations. daisy-chaining minimizes the number of port pins required from the controlling ic (see figure 5). the sdo pin contains an open drain n-channel fet that requires a pull-up resistor if this function is used. as shown in figure 5, users need to tie the sdo pin of one pack age to the sdi pin of the next package. users may need to increase the clock period because the pull-up resistor and the capacitive loading at the sdo-sdi interface may require additional time delay between subsequent packages. if two ad5232? are daisy-chained, 32 bits of data are required. the first 16 bits go to u2 and the second 16 bits w ith the same format go to u1. the 16 bits are formatted to contain the 4-bit instruction, followed by the 4-bit address, then the 8 bits of data. the cs should be kept low until all 32 bits are locked into their respective serial registers. the cs is then pulled high to complete the operation. sdi sdo clk +v r p 2k c sdi sdo clk cs cs u1 u2 ad5232 ad5232 figure 5. daisy-chain configuration using sdo microconverter is a registered trademark of analog devices, inc. table ii. 16-bit serial data word msb b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 lsb ad5232 c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 command bits are identified as cx, address bits are ax, and data bits are dx. command instruction codes are defined in table iii.
rev. 0 ad5232 C9C table iii. instruction/operation truth table instruction byte 1 data byte 0 inst b15 b8 b7 b0 no. c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0000 xxxx xx x xxxx x no o peration (nop). do nothing. 1 0001000a0 xx x x xxx x write contents of eemem(a0) to rdac(a0) register. this command leaves device in the read program power state. to return part to the idle state, perform nop instruction #0. 2 0010000a0 xx x x xxx x save wiper setting. write con- tents of rdac(addr) to eemem(a0) 3 0011 << addr >> d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data byte 0 to eemem(addr). 4 0100000a0 xxxxxxxx d ecrement 6 db right shift contents of rdac(a0), stops at all ?eros. 5 0101 xxxx xxxxxxxx decrement all 6 db right shift contents of all rdac registers, stops at all ?eros. 6 0110000a0 xxxxxxxx d ecrement contents of rdac(a0) by ?ne,?stops at all ?eros. 7 0111 xxxx xxxxxxxx d ecrement contents of all rdac regis- ters by ?ne,?stops at all ?eros. 8 10000000 xxxxxxxx reset. load all rdacs with their cor- responding eemem previously-saved values. 9 1001 << addr >> xxxxxxxx w rite contents of eemem(addr) to serial register data byte 0. 10 1010000a0 xxxxxxxx w rite contents of rdac(a0) to serial register data byte 0. 11 1011000a0 d7d6d5d4d3d2d1d0 w rite contents of serial register data byte 0 to rdac(a0). 12 1100000a0 xxxxxxxx in crement 6 db left shift contents of rdac(a0), stops at all ?nes. 13 1101 xxxx xxxxxxxx increment all 6 db left shift contents of all rdac registers, stops at all ?nes. 14 1110000a0 xxxxxxxx in crement contents of rdac(a0) by ?ne,?stops at all ?nes. 15 1111 xxxx xxxxxxxx in crement contents of all rdac regis- ters ?ne,?stops at all ?nes. notes 1. the sdo output shifts out the last eight bits of data clocked into the serial register for daisy-chain operation. exception: following instruction #9 or #10 the selecte d internal register data will be present in data byte 0. instructions following #9 and #10 must be a full 16-bit data word to completely c lock out the contents of the serial register. 2. the rdac register is a volatile scratch pad register that is refreshed at power-on from the corresponding nonvolatile eemem register. 3. the increment, decrement, and shift commands ignore the contents of the shift register data byte 0. 4. execution of the operation column noted in the table takes place when the cs strobe returns to logic high. 5. execution of a nop instruction minimizes power dissipation.
rev. 0 C10C ad5232 also the left shift commands were modified so that if the data in the rdac register is greater than or equal to midscale and the data is left shifted then the data in the rdac register is set to full-scale. this makes the left shift function as close to ideally logarithmic as is possible. the right shift #4 and #5 commands will be ideal only if the lsb is zero (i.e., ideal logarithmic?o error). if the lsb is a one then the right shift function generates a linear half lsb error, which translates to a code dependent logarithmic error for odd codes only as shown in the attached plots, (see figure 5). the plot shows the errors of the odd codes for the ad5232. 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 1111 1111 1111 1111 left shift 1111 1111 0111 1111 0011 1111 0001 1111 0000 1111 0000 0111 0000 0011 0000 0001 0000 0000 0000 0000 0000 0000 right shift left shift (+6 db) right shift ( 6 db) figure 6. detail left and right shift function for the 8-bit ad5232 actual conformance to a logarithmic curve between the data contents in the rdac register and the wiper position for each right shift #4 and #5 command execution contains an error only for the odd codes. even codes are ideal except zero right shift or greater than half-scale left shift. the graph in figure 7 shows plots of log_error [i.e., 20 log 10 (error/code)]. for example, code 3 log_error = 20 log 10 (0.5/3) = ?5.56 db, which is the worst case. the plot of log_error is more signifi- cant at the lower codes. code, from 1 to 255 by 2 20 40 60 80 100 0 120 140 160 180 200 220 240 260 0 10 20 30 40 50 60 db log_error (code) for 8-bit figure 7. plot of log_error conformance for odd codes only (even codes are ideal) advanced control modes the ad5232 digital potentiometer contains a set of user program- ming features to address the wide applications available to these universal adjustment devices. key programming features include: independently programmable read and write to all registers. ? simultaneous refresh of all rdac wiper registers from corresponding internal eemem registers. ? increment and decrement instructions for each rdac wiper register. ? left and right bit shift of all rdac wiper registers to achieve 6 db level changes. ? nonvolatile storage of the present scratch pad rdac register values into the corresponding eemem register. ? fourteen extra bytes of user-addressable electrical-erasable memory. increment and decrement commands the increment and decrement commands (#14, #15, #6, #7) are useful for the basic servo adjustment application. this com- mand simplifies microcontroller software coding by eliminating the need to perform a readback of the current wiper position, then add one to the register contents using the microcontroller? adder. the microcontroller simply sends an increment command (#14) to the digital pot, which will automatically move the wiper to the next resistance segment position. the master incre- ment command (#15) will move all pot wipers by one position from their present position to the next resistor segment position. the direction of movement is referenced to terminal b. thus each increment #15 command will move the wiper tap position farther away from terminal b. logarithmic taper mode adjustment programming instructions allow a decrement and an increment wiper position control by individual pot or in a ganged pot arrangement where both wiper positions are changed at the same time. these settings are activated by the 6 db decrement and 6 db increment instructions #4 and #5 and #12 and #13 respectively. for example, starting with the wiper connected to terminal b executing nine increment instructions (#12) would move the wiper in +6 db steps from the 0% of r ba (b terminal) position to the 100% of r ba position of the ad5232 8-bit potentiometer. the 6 db increment instruction doubles the value of the rdac register contents each time the command is executed. when the wiper position is greater than midscale, the last 6 db increment instruction will cause the wiper to go to the full-scale 255 code position. any additional +6 db instruction will no longer change the wiper position from full scale (rdac register code = 255). figure 6 illustrates the operation of the 6 db shifting function on the individual rdac register data bits for the 8-bit ad5232 example. each line going down the table represents a successive shift operation. very important: the left shift #12 and #13 com- mands were modified so that if the data in the rdac register is equal to zero and the data is left shifted, it is then set to code 1.
rev. 0 ad5232 C11C using additional internal nonvolatile eemem the ad5232 contains additional internal user storage registers (eemem) for saving constants and other 8-bit data. table iv provides an address map of the internal nonvolatile storage registers shown in the functional block diagram as eemem1, eemem2, and bytes of user eemem. table iv. eemem address map eemem eemem contents of each address device eemem (addr) (addr) ad5232 (8b) 0000 rdac1 0001 rdac2 0010 user 1 0011 user 2 0100 user 3 0101 user 4 *** *** 1111 user 14 notes 1 rdac data stored in eemem locations are transferred to their corresponding rdac register at power on, or when instructions inst#1 and inst#8 are executed. 2 user is internal nonvolatile eemem registers available to store and retrieve constants using inst#3 and inst#9 respectively. 3 ad5232 eemem locations are 1 byte each (8 bits). 4 execution of instruction #1 leaves the device in the read mode power con- sumption state. after the last instruction #1 is executed, the user should perform a nop, instruction #0 com mand to return the device to the low power idle state. v dd a w b v ss figure 8. maximum terminal voltages set by v dd and v ss detail potentiometer operation the actual structure of the rdac is designed to emulate the performance of a mechanical potentiometer. the patent-pending rdac contains multiple strings of connected resistor segments, with an array of analog switches that act as the wiper connection to several points along the resistor array. the number of points is the resolution of the device. for example, the ad5232 has 256 connection points allowing it to provide better than 0.5% setability resolution. figure 9 provides an equivalent dia- gram of the connections between the three terminals that make up one channel of the rdac. the sw a and sw b will always be on, while one of the switches sw(0) to sw(2 n ?) will be on one at a time depending upon the resistance step decoded from the data bits. the resistance contributed by r w must be accounted for in the output resistance. the sw a and sw b will always be on while one of the switches sw(0) to sw(2 n ?) will be on one at a time, depending upon the resistance step decoded from the data bits. the resistance contributed by r w must be accounted for in the output resistance. sw a sw(2 n 1) a x w x sw(2 n 2) sw (1) sw (0) sw b b x rdac wiper register and decoder r s = r ab /2 n r s r s r s digital circuitry omitted for clarity figure 9. equivalent rdac structure (patent pending) table v. rdac and digital register address map register address name of register * (addr) ad5232 (8b) 0000 rdac1 0001 rdac2 * rdacx registers contain data determining the position of the variable resistor wiper. terminal voltage operating range the digital potentiometer? positive v dd and negative v ss power supply defines the boundary conditions for proper three-terminal programmable resistance operation. signals present on terminals a, b, w that exceed v dd or v ss will be clamped by a forward biased diode; see figure 8. the ground pin of the ad5232 device is primarily used as a digital ground reference, which needs to be tied to the pcbs common ground. the digital input logic signals to the ad5232 must be referenced to the devices?ground pin (gnd), and satisfy the logic minimum input high level and the maximum low level defined in the specification table of this data sheet. an internal level-shift circuit between the digital interface and the wiper switch control ensures that the common-mode voltage range of the three-terminals a, w, and b extends from v ss to v dd .
rev. 0 C12C ad5232 table vi. nominal individual segment resistor values ( ) segment resistor size for r ab end-to-end values 10 k version 50 k version 100 k version 8-bit 78.10 390.5 781.0 programming the variable resistor rheostat operation the nominal resistances of the rdac between terminals a and b are available with values of 10 k ? , 50 k ? , and 100 k ? . the final digits of the part number determine the nominal resistance value, e.g., 10 k ? = 10; 100 k ? = 100. the nominal resistance (r ab ) of the ad5232 vr has 256 contact points accessed by the wiper terminal, plus the b terminal contact. the 8-bit data word in the rdac latch is decoded to select one of the 256 possible settings. the general transfer equation, which determines the digitally programmed output resistance between wx and bx, is: r wb (dx) = (dx) / 2 n r ba + r w (1) where n is the resolution of the vr, dx is the data contained in the rdacx latch, and r ba is the nominal end-to-end resistance. for example, the following output resistance values will be set for the following rdac latch codes (applies to the 8-bit, 10 k ? potentiometers): table vii. nominal resistance value at selected codes for r ab = 10 k d (dec) r wb (v) output state 255 10011 full-scale 128 5050 midscale 1891 lsb 0 50 zero-scale * (wiper contact resistance) * note that in the zero-scale condition a finite wiper resistance of 50 ? is present. care should be taken to limit the current flow between w and b in this state to a maximum continuous value of 2 ma to avoid degradation or possible de struc- tion of the internal switch metalization. intermittent current operation to 20 ma is allowed. code decimal 100 75 0 0 256 64 percent of nominal end-to-end resistance % r ab 128 192 50 25 r wb r wa figure 10. symmetrical rdac operation like the mechanical potentiometer the rdac replaces, the ad5232 parts are totally symmetrical. the resistance between the wiper w and terminal a also produces a digitally controlled resistance r wa . figure 10 shows the symmetrical programmabil- ity of the various terminal connections. when these terminals are used the b?erminal should be tied to the wiper. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. the general transfer equation for this operation is: r wa (dx) = (2 n -dx) / 2 n r ba + r w (2) where n is the resolution of the vr, dx is the data contained in the rdacx latch, and r ba is the nominal end-to-end resistance. for example, the following output resistance values will be set for the following rdac latch codes (applies to 8-bit, 10 k ? potentiometers). table viii. nominal resistance value at selected codes for r ab = 10 k d (dec) r wa (w) output state 255 89 full-scale 128 5050 midscale 1 10011 1 lsb 0 10050 zero-scale the multichannel ad5232 has a 0.2% typical distribution of internal channel-to-channel r ba match. device-to-device matching is process-lot-dependent and exhibits a ?0% to +20% variation. the change in r ba with temperature has a 600 ppm/ c temperature coefficient. device resolution
rev. 0 ad5232 C13C programming the potentiometer divider voltage output operation the digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. for example, connecting a-terminal to 5 v and b-terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 5 v. each lsb of voltage is equal to the voltage applied across terminal ab divided by the 2 n position resolution of the potentiometer divider. the general equation defining the output voltage with respect to ground for any given input voltage applied to terminals ab is: v w (dx) = dx / 2 n v ab + v b (3) operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. here the output volt age is dependent on the ratio of the internal resistors, not the absolute value; therefore, the drift improves to 15 ppm/ c. there is no volt age polarity restriction between terminals a, b, and w, as long as the terminal voltage (v term ) stays within v ss < v term < v dd . operation from dual supplies the ad5232 can be operated from dual supplies enabling con- trol of ground-referenced ac signals. see figure 11 for a typical circuit connection. ~ 2v p-p ad5232 v ss gnd sdi clk ss sclk mosi gnd v dd c 1v p-p v dd +2.75v 2.5v cs figure 11. operation from dual supplies c a ab c b c w rdac 10k w 60pf c a = 45pf c b = 45pf figure 12. rdac circuit simulation model for rdac = 10 k ? the internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the rdacs. configured as a potentiometer divider the ? db bandwidth of the ad5232bru10 (10 k ? resistor) measures 500 khz at half scale. figure tpc 10 provides the large signal bode plot characteristics of the three resistor versions 10 k ? , 50 k ? , and 100 k ? . a parasitic simu- lation model has been developed, and is shown in figure 12. listing i provides a macro model net list for the 10 k ? rdac: listing i. macro model net list for rdac .param dw=255, rdac=10e3 * .subckt dpot (a,w,b) * ca a 0 {45e-12} raw a w {(1-dw/256)*rdac+50} cw w 0 60e-12 rbw w b {dw/256*rdac+50} cb b 0 {45e-12} * .ends dpot application programming examples the following command sequence examples have been developed to illustrate a typical sequence of events for the various features of the ad5232 nonvolatile digital potentiometer. [pcb = printed circuit board containing the ad523x part]. instruction numbers (commands), addresses and data appear- ing at sdi and sdo pins are listed in hexadecimal. table ix. set two digital pots to independent data values sdi sdo action b140 h xxxx h loads 40 h data into rdac2 register, wiper w2 moves to 1/4 full-scale position. b080 h b140 h loads 80 h data into rdac1 register, wiper w1 moves to 1/2 full-scale position.
rev. 0 C14C ad5232 table x. active trimming of one pot followed by a save to nonvolatile memory (pcb calibrate) sdi sdo action b040 h xxxx h loads 40 h data into rdac1 register, wiper w1 moves to 1/4 full-scale position. e0xx h b040 h increments rdac1 register by one to 41 h , wiper w1 moves one resistor segment away from terminal b. e0xx h e0xx h increments rdac1 register by one to 42 h , wiper w1 moves one more resistor segment away from terminal b. continue until desired wiper position reached. 20xx h e0xx h saves rdac1 register data into corresponding nonvolatile eemem1 memory addr = 0 h . equipment customer startup sequence for a pcb calibrated unit with protected settings pcb setting: tie wp to gnd [prevents changes in pcb wiper set position] power v dd and v ss with respect to gnd optional: strobe pr pin [ensures full power on preset of wiper register with eemem contents in unpredictable supply sequencing environments] table xi. using left shift by one to change circuit gain in 6 db steps sdi sdo action c1xx h xxxx h moves wiper w2 to double the present data value contained in rdac2 regis- ter, in the direction of the a terminal. c1xx h xxxx h moves wiper w2 to double the present data value contained in rdac2 regis- ter, in the direction of the a terminal. table xii. storing additional data in nonvolatile memory sdi sdo action 3280 h xxxx h stores 80 h data into spare eemem location user1. 3340 h xxxx h stores 40 h data into spare eemem location user2. table xiii. reading back data from various memory locations sdi sdo action 94xx h xxxx h prepares data read from user3 location. assumption: user3 previously loaded with 80 h . 00xx h xx80 h nop instruction #0 sends 16-bit word out of sdo where the last 8 bits con- tain the contents of user3 location. nop command ensures device returns to idle power dissipation state. analog devices offers the ad5232eval board for sale to simplify evaluation of these programmable devices controlled by a personal computer via the printer port. test circuits figures 13 to 22 define the test conditions used in the product specification? table. a w b nc i w dut v ms nc = no connect figure 13. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) a w b dut v ms v+ v+ = v dd 1lsb = v+/2 n figure 14. potentiometer divider nonlinearity error test circuit (inl, dnl) a w b dut i w v ms1 v ms2 v w r w = [ v ms1 v ms2 ] /i w figure 15. wiper resistance test circuit a w b v ms v+ = v dd 10% psrr (db) = 20 log v ms v dd ( ) ~ v a v dd v ms % v dd % pss (%/%) = v+ figure 16. power supply sensitivity test circuit (pss, psrr) ~ offset bias offset gnd ab dut w 5v v in v out op279 figure 17. inverting gain test circuit
rev. 0 ad5232 C15C ~ offset bias offset gnd ab dut w 5v v in v out op279 figure 18. noninverting gain test circuit ~ offset gnd a b dut w +15v v in v out op42 15v 2.5v figure 19. gain vs. frequency test circuit + _ dut code = oo h 0.1v v ss to v dd r sw = 0.1v i sw i sw w b figure 20. incremental on resistance test circuit dut v ss i cm w b v dd nc nc v cm gnd a nc = no connect figure 21. common-mode leakage current test circuit w2 b2 v dd a2 ~ v in nc w1 rdac 1 a1 b1 v ss v out rdac 2 c ta = 20 log [ v out /v in ] figure 22. analog crosstalk test circuit flash/eemem reliability the flash/ee memory array on the ad5232 is fully qualified for two key flash/ee memory characteristics, namely flash/ee memory cycling endurance and flash/ee memory data retention. endurance quantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cycles. in real terms, a single endurance cycle is composed of four indepen- dent, sequential events. these events are defined as: a. initial page erase sequence b. read/verify sequence c. byte program sequence d. second read/verify sequence during reliability qualification flash/ee memory is cycled from 00 h to ff h until a first fail is recorded, signifying the endurance limit of the on-chip flash/ee memory. as indicated in the specification pages of this data sheet, the ad5232 flash/ee memory endurance qualification has been carried out in accordance with jedec specification a117 over the industrial temperature range of ?0 c to +85 c. the results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25 c. retention quantifies the ability of the flash/ee memory to retain its programmed data over time. again, the ad5232 has been qualified in accordance with the formal jedec retention life- time specification (a117) at a specific junction temperature (t j = 55 c). as part of this qualification procedure, the flash/ee memory is cycled to its specified endurance limit described above, before data retention is characterized. this means that the f lash/ee memory is guaranteed to retain its data for its full-specified reten- tion lifetime every time the flash/ee memory is repro grammed. it should also be noted that retention lifetime, based on an activa- tion energy of 0.6 ev, will derate with t j as shown in figure 23. t j junction temperature c 300 250 0 40 retention years 200 150 100 50 50 60 70 80 90 100 110 adi typical performance at t j = 55 c figure 23. flash/ee memory data retention
rev. 0 C16C ad5232 digital code 2.00 0.50 2.00 0 iinl error lsb 1.50 0 1.00 1.50 1.00 0.50 64 128 192 1.75 1.25 0.75 0.25 0.75 1.25 1.75 0.25 inl t a = 40 c inl t a = +85 c inl t a = +25 c 256 v dd = 2.7v v ss = 0v tpc 1. inl vs. code, t a = C40 c, +25 c, +85 c overlay digital code 2.00 0.50 2.00 1 dnl error lsb 1.50 0 1.00 1.50 1.00 0.50 64 128 192 1.75 1.25 0.75 0.25 0.75 1.25 1.75 0.25 dnl t a = 40 c dnl t a = +25 c dnl t a = +85 c 256 v dd = 2.7v v ss = 0v tpc 2. dnl vs. code, t a = C40 c, +25 c, +85 c overlay code decimal 0.20 0.20 0 32 64 96 128 0.15 0.00 0.05 0.10 0.15 0.10 0.05 160 192 224 256 v dd = 5.5v, v ss = 0v t a = 25 c r-dnl lsb tpc 3. r-dnl vs. code r ab = 10 k ? , 50 k ? , 100 k ? overlay 2000 0 032 rheostat mode tempco ppm/ c 64 96 128 160 1000 500 1500 192 224 256 code decimal t a = 40 c/+85 c v a = no connect r wb measured v dd = 5v tpc 4. ? r wb / ? t vs. code r ab = 10 k ? , v dd = 5 v 70 032 potentiometer mode tempco ppm/ c 64 96 128 160 192 224 256 v dd = 5v t a = 40 c/+85 c v a = 2.00v v b = 0v 10 60 30 20 10 0 50 40 code decimal tpc 5. ? v wb / ? t vs. code r ab = 10 k ? , v dd = 5 v 0.001 50 35 i cm a 20 510 25 0.01 40 55 70 temperature c 0.1 1 85 v dd = +2.5v v cm = 0v v ss = 2.5v see figure 21 tpc 6. i cm vs. temperature typical performance characteristics
rev. 0 ad5232 C17C 50 35 i dd a 20 510 25 2 40 55 70 temperature c 4 85 v dd = 5.5v v dd = 2.7v tpc 7. i dd vs. temperature tpc 8. i dd vs. time (save) program mode frequency hz 12 6 42 1k 10k gain db 0 6 30 12 18 24 36 100k 1m f 3db = 500khz, r = 10k v in = 100mv rms v dd = +2.5v, v ss = 2.5v r l = 1m f 3db = 45khz, r = 100k f 3db = 95khz, r = 50k t a = 25 c -+%# ')77 frequency hz 10 10 thd + noise % 1 0.1 0.01 0.001 100 1k 10k 100k r ab = 10k r ab = 50k , 100k t a = 25 c v dd = 5v filter = 22khz tpc 11. total harmonic distortion vs. frequency code 0 1 r w 64 128 192 10 20 30 40 50 60 70 80 90 100 110 256 t a = 25 c v dd = 2.7v -+%#( @
&3 % -+%6 -<
rev. 0 C18C ad5232 frequency hz 0 60 1k gain db 30 100k 10k 6 36 42 48 54 24 12 18 1m v dd = +2.7v v ss = 2.7v v a = 100mv rms t a = 25 c v a data = 80 h data = 40 h data = 20 h data = 10 h data = 08 h data = 04 h data = 02 h data = 01 h r ab = 10k tpc 13. gain vs. frequency vs. code, r ab = 10 k ? frequency hz 0 60 1k gain db 30 100k 10k 6 36 42 48 54 24 12 18 1m v dd = +2.7v v ss = 2.7v v a = 100mv rms t a = 25 c v a data = 80 h data = 40 h data = 20 h data = 10 h data = 08 h data = 04 h data = 02 h data = 01 h r ab = 50k tpc 14. gain vs. frequency vs. code, r ab = 50 k ? frequency hz 0 60 1k gain db 30 100k 10k 6 36 42 48 54 24 12 18 1m v dd = +2.7v v ss = 2.7v v a = 100mv rms t a = 25 c v a data = 80 h data = 40 h data = 20 h data = 10 h data = 08 h data = 04 h data = 02 h data = 01 h r ab = 100k tpc 15. gain vs. frequency vs. code, r ab = 100 k ? frequency hz 80 0 1k psrr rejection db 40 100k 10k 20 1m 60 t a = 25 c v dd = 5.5v 100mv ac v ss = 0v, v b = 5v, v a = 0v measure at v w with code = 80 h r ab = 100k r ab = 50k r ab = 10k tpc 16. psrr vs. frequency frequency khz 120 20 1 c ta analog crosstalk rejection db 60 10 40 100 80 v dd = v a2 = +2.75v v ss = v b2 = 2.75v v in = +2.5v p r ab = 100k r ab = 50k r ab = 10k see test circuit, figure 22 100 t a = 25 c -+%#0 %
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rev. 0 ad5232 C19C number resolution power of vrs terminal interface nominal (number supply part per voltage data resistance of wiper current number package range (v) control (k ) positions) (i dd )( a) packages comments ad5201 1 3, +5.5 3-wire 10, 50 33 40 soic-10 full ac specs, dual supply, pwr-on-reset, low cost ad5220 1 5.5 up/ 10, 50, 100 128 40 pdip, so-8, no rollover, down soic-8 pwr-on-reset ad7376 1 15 , +28 3-wire 10, 50, 100, 1000 128 100 pdip-14, single 28 v sol-16, or dual 15 v tssop-14 supply operation ad5200 1 3 , +5.5 3-wire 10, 50 256 40 soic-10 full ac specs, dual supply, pwr-on-reset ad8400 1 5.5 3-wire 1, 10, 50, 100 256 5 so-8 full ac specs ad5260 1 5, +15 3-wire 20, 50, 200 256 60 tssop-14 +5 v to +15 v or 5 v operation, tc < 50 ppm/ c ad5241 1 3, +5.5 2-wire 10, 100, 1000 256 50 so-14, i 2 c compatible, tssop-14 tc < 50 ppm/ c ad5231 1 2.75, +5.5 3-wire 10, 50, 100 1024 10 tssop-16 nonvolatile mem ory, direct program, i/d, 6 db settability ad5222 2 3, +5.5 up/ 10, 50, 100, 1000 128 80 so-14, no rollover, stereo, down tssop-14 pwr-on-reset, tc < 50 ppm/ c ad8402 2 5.5 3-wire 1, 10, 50, 100 256 5 pdip, so-14, full ac specs, na tssop-14 shutdown current ad5207 2 3, +5.5 3-wire 10, 50, 100 256 40 tssop-14 full ac specs, dual supply, pwr-on- reset, sdo ad5232 2 2.75, +5.5 3-wire 10, 50, 100 256 10 tssop-16 n onvolatile m emory, direct program, i/d, 6 db settability ad5235 * 2 2.75, +5.5 3-wire 25, 250 1024 20 tssop-16 nonvolatile memory, direct program, tc < 50 ppm/ c ad5242 2 3, +5.5 2-wire 10, 100, 1000 256 50 so-16, i 2 c compatible, tssop-16 tc < 50 ppm/ c ad5262 * 2 5, +15 3-wire 20, 50, 200 256 60 tssop-16 +5 v to +15 v or 5 v operation, tc < 50 ppm/ c ad5203 4 5.5 3-wire 10, 100 64 5 pdip, sol-24, full ac specs, na tssop-24 s hutdown current ad5233 4 2.75, +5.5 3-wire 10, 50, 100 64 10 tssop-16 nonvolatile memory, direct program, i/d, 6 db settability ad5204 4 3, +5.5 3-wire 10, 50, 100 256 60 pdip, sol-24, full ac specs, tssop-24 dual supply, pwr-on-reset ad8403 4 5.5 3-wire 1, 10, 50, 100 256 5 pdip, sol-24, full ac specs, na tssop-24 shutdown current ad5206 6 3, +5.5 3-wire 10, 50, 100 256 60 pdip, sol-24, full ac specs, tssop-24 dual supply, pwr-on-reset * future product, consult factory for latest status. latest digital potentiometer information located at: www.analog.com/digitalpotentiometers digital potentiometer family selection guide
rev. 0 C20C c02618C1C10/01(0) printed in u.s.a. ad5232 outline dimensions dimensions shown in inches and (mm). printed in u.s.a. 16-lead tssop (ru-16) 16 9 8 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.201 (5.10) 0.193 (4.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0

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